Quantum Computing Architectures: Superconducting Qubits, Trapped Ions, and the NISQ Era

2025-04-17 · Leonardo Benicio

From transmon Hamiltonians to Majorana zero modes — a deep architectural dive into the physical platforms competing to build the first fault-tolerant quantum computer, and why the error correction overhead dominates everything.

Quantum computing occupies a strange place in the computing landscape. On one hand, it is the subject of breathless press releases claiming quantum supremacy, quantum advantage, and the imminent obsolescence of all classical cryptography. On the other hand, the largest quantum computers in existence have on the order of 1,000 physical qubits, can execute perhaps a few hundred coherent operations before decoherence destroys the quantum state, and have yet to solve a single commercially valuable problem faster than a classical computer. Both of these statements are true, and that tension — between the theoretical promise and the practical reality — is what makes quantum computing the most fascinating, and most misunderstood, field in computer architecture today.

This post is a systems-level introduction to quantum computing architectures. I am not going to teach you quantum mechanics from first principles — there are excellent resources for that, from Nielsen and Chuang’s canonical textbook to the online lecture notes of John Preskill. Instead, I am going to focus on the architectural questions that a systems researcher would ask: What are the physical substrates that can host a qubit? How do you perform gates on them? How do you connect them into a larger processor? And, most critically, how do you deal with errors — because in quantum computing, errors are not a rare exception, they are the dominant constraint on everything?

We will examine three leading qubit technologies: superconducting transmon qubits (the approach taken by IBM, Google, and Rigetti), trapped-ion qubits (Quantinuum, IonQ), and topological qubits (Microsoft’s bet, still in the experimental stage). For each, we will look at the physics, the gate fidelity, the connectivity, and the scaling prospects. Then we will tackle the elephant in the room: quantum error correction, which turns physical qubits with error rates of (10^{-3}) per gate into logical qubits with error rates of (10^{-15}) or better, at the cost of a thousandfold overhead. And finally, we will assess where we are in the so-called NISQ (Noisy Intermediate-Scale Quantum) era and what it will take to get to fault tolerance.

1. What Is a Qubit, Architecturally Speaking?

Architecturally, the challenge is to find a physical system that can (a) be initialized to a known state, (b) be manipulated with high fidelity to perform quantum gates, (c) maintain quantum coherence long enough to complete a computation, and (d) be read out at the end. These requirements are captured in the DiVincenzo criteria, proposed by David DiVincenzo in 2000:

A scalable physical system with well-characterized qubits.
The ability to initialize the qubit state to (|0\rangle).
Long relevant coherence times, much longer than the gate operation time.
A universal set of quantum gates.
A qubit-specific measurement capability.

And for quantum communication, two additional criteria:

The ability to interconvert stationary and flying qubits.
The ability to faithfully transmit flying qubits between locations.

Every qubit technology represents a different trade-off across these criteria. Superconducting qubits have fast gates (10-100 ns) but short coherence times (50-100 μs). Trapped ions have slow gates (10-100 μs) but extraordinarily long coherence times (seconds to minutes). Topological qubits, if they can be built, would have intrinsically low error rates but are far harder to manipulate. The search for the “Goldilocks” qubit — fast, coherent, manufacturable, and scalable — is the central architectural challenge of quantum computing.

2. Superconducting Qubits: The Transmon and Its Cousins

Superconducting qubits are the most widely used technology today, powering IBM’s Quantum System Two (1,121 qubits in the Condor processor, announced 2023), Google’s Sycamore (53 qubits, the chip that claimed quantum supremacy in 2019) and Willow (105 qubits, 2024), and Rigetti’s Aspen-M (80 qubits). They are fabricated on silicon wafers using techniques borrowed from the semiconductor industry — aluminum or niobium circuits patterned by optical lithography — which gives them a natural scaling advantage.

The transmon (transmission-line shunted plasma oscillation qubit) is the dominant superconducting qubit design. It was developed at Yale in 2007 by the group of Robert Schoelkopf and Michel Devoret, building on earlier work on the Cooper pair box. The key innovation of the transmon is that it drastically reduces sensitivity to charge noise — the dominant source of decoherence in early superconducting qubits — by shunting the Josephson junction with a large capacitance.

Here is the circuit diagram of a transmon:

                    C_shunt
                 +----||----+
                 |          |
    +------------+          +------------+
    |                                    |
    |          +------+------+           |
    |          |             |           |
    |      Josephson     Josephson       |
    |      Junction      Junction        |
    |          |             |           |
    |          +------+------+           |
    |                                    |
    +----------------+-------------------+
                     |
                   Ground

The Josephson junction is the essential nonlinear element. It consists of two superconducting electrodes separated by a thin insulating barrier (typically aluminum oxide, ~1 nm thick). The junction behaves as a nonlinear inductor: its inductance depends on the current flowing through it, which makes the energy levels of the circuit anharmonic — the energy difference between the (|0\rangle \rightarrow |1\rangle) transition is different from the (|1\rangle \rightarrow |2\rangle) transition. This anharmonicity is what allows us to address the qubit without accidentally exciting it to higher states. The transmon operates in the regime where the Josephson energy (E_J) dominates the charging energy (E_C) (typically (E_J/E_C \approx 50)-(100)), which flattens the energy bands and makes the qubit frequency insensitive to charge fluctuations.

Gates on a transmon qubit are performed by applying microwave pulses at the qubit’s resonant frequency (typically 4-6 GHz). A resonant pulse of appropriate duration and phase implements a rotation around an axis in the equatorial plane of the Bloch sphere — this is a single-qubit gate. The pulse shape is carefully engineered (typically Gaussian or DRAG — Derivative Removal by Adiabatic Gate) to minimize leakage to the (|2\rangle) state and to avoid exciting neighboring qubits.

Two-qubit gates are more challenging. The most common approach is the cross-resonance (CR) gate, where one qubit (the control) is driven at the frequency of another qubit (the target). Because the qubits are coupled — either capacitively or through a shared resonator — the drive induces a conditional rotation on the target qubit that depends on the state of the control. This implements a (ZX_{\theta}) interaction, which, combined with single-qubit rotations, yields a universal gate set. The CR gate takes about 100-400 ns and currently achieves fidelities of 99.0-99.9% in state-of-the-art devices.

The physical layout of superconducting qubits is a planar graph. Here is a simplified 2D grid:

    Q0 --- Q1 --- Q2 --- Q3
     |      |      |      |
    Q4 --- Q5 --- Q6 --- Q7
     |      |      |      |
    Q8 --- Q9 --- Q10 --- Q11

Each node is a transmon qubit. Each edge is a coupling resonator (a section of coplanar waveguide) that allows two-qubit gates between adjacent qubits. Long-range interactions require SWAP gates to move quantum information across the grid. This limited connectivity — typically 2-4 neighbors per qubit — is a major constraint on quantum algorithm compilation. A circuit that requires all-to-all connectivity must be transpiled into a circuit that respects the hardware topology, adding SWAP gates that consume precious coherence time and degrade fidelity.

The dominant source of error in superconducting qubits is decoherence: the qubit loses its quantum information to the environment. There are two mechanisms. (T_1) (energy relaxation) is the decay of the excited state (|1\rangle) to the ground state (|0\rangle), caused by the qubit emitting a photon into its environment. (T_2) (dephasing) is the loss of phase coherence between (|0\rangle) and (|1\rangle), caused by fluctuations in the qubit frequency due to charge noise, flux noise, or photon shot noise in the readout resonator. The coherence time (T_2) is typically 50-200 μs for state-of-the-art transmons, which, given gate times of 20-50 ns, allows for 2,000-10,000 gate operations before the qubit decoheres. This is the fundamental performance envelope of superconducting quantum processors.

3. Trapped-Ion Qubits: Precision at the Cost of Speed

Trapped-ion quantum computers take a fundamentally different approach. Instead of fabricating qubits on a chip, they suspend individual ions (typically ytterbium-171 or calcium-40) in a vacuum, confined by electric fields in a linear Paul trap. Each ion encodes a qubit in two of its internal energy levels — typically two hyperfine ground states (for ytterbium, (|0\rangle = |F=0, m_F=0\rangle) and (|1\rangle = |F=1, m_F=0\rangle)), which are separated by a microwave-frequency transition (12.6 GHz for Yb-171) and have coherence times measured in seconds.

The ions form a linear chain, held in place by a combination of radio-frequency (RF) and DC electric fields:

    +--------------------------------------------------+
    |                   Vacuum Chamber                  |
    |   +------------------------------------------+   |
    |   |  DC Electrode  |  RF Electrode | DC Elec. |   |
    |   +--------+-------+--------+------+----+-----+   |
    |            |                |           |         |
    |     *------*------*---------*----*------*------*  |
    |    Ion0   Ion1   Ion2     Ion3  Ion4   Ion5   Ion6|
    |            |                |           |         |
    |   +--------+-------+--------+------+----+-----+   |
    |   |             Laser Beams              |         |
    +------------------------------------------+---------+

Single-qubit gates are performed by illuminating an ion with a focused laser beam (or a microwave field). A laser pulse of controlled duration, phase, and intensity drives Rabi oscillations between (|0\rangle) and (|1\rangle), implementing an arbitrary rotation on the Bloch sphere. The gate fidelity for single-qubit operations on trapped ions exceeds 99.99% — essentially perfect by current standards.

Two-qubit gates exploit the shared motional modes of the ion chain. Because the ions are charged and repel each other, they cannot move independently; instead, they oscillate collectively in normal modes (like masses connected by springs). The Mølmer-Sørensen gate illuminates two ions simultaneously with bichromatic laser beams that are slightly detuned from the qubit transition. The lasers couple the qubit states to a shared motional mode, creating an effective interaction that entangles the two qubits. The gate time is proportional to the motional mode period, typically 10-100 μs. The fidelity of two-qubit gates on trapped ions is currently the best of any platform: Quantinuum’s H2 processor reports 99.8% two-qubit gate fidelity, and IonQ reports similar numbers.

The key advantage of trapped ions is connectivity. Because the motional modes are shared across the entire chain, any ion can interact with any other ion — this is effectively all-to-all connectivity, without the SWAP overhead of superconducting grids. This is a huge architectural advantage: quantum algorithms that require dense connectivity (like the Quantum Approximate Optimization Algorithm, QAOA) can be mapped to trapped ions with far lower overhead than superconducting qubits.

The key disadvantage is speed. Trapped-ion gates are 1,000-10,000 times slower than superconducting gates (microseconds vs. nanoseconds). This is not necessarily a problem for algorithm runtime — the total number of gates that can be performed before decoherence is the relevant metric, not the absolute gate speed — but it does affect practical throughput for near-term applications. A circuit with 10,000 gates takes about 0.2 seconds on a trapped-ion processor, during which time environmental noise (magnetic field fluctuations, laser intensity drift) can cause errors.

Scaling trapped ions is another challenge. Current systems have about 20-50 ions per trap. To scale to thousands of qubits, Quantinuum is developing a “quantum charge-coupled device” (QCCD) architecture, where ions are shuttled between different trapping zones by time-varying electric potentials. Ions in a “memory zone” store quantum information. Ions in a “gate zone” interact to perform gates. The shuttling — physically moving the ions around — takes about 100-300 μs and has a fidelity of 99.9% or better. This is the trapped-ion equivalent of a memory hierarchy, and it is one of the most promising approaches to scaling beyond the single-trap limit.

4. Topological Qubits: The Holy Grail

If superconducting qubits are the workhorses of the NISQ era and trapped ions are the thoroughbreds, topological qubits are the unicorns. They do not yet exist in a form that can perform a single coherent gate, but the potential payoff is so large that Microsoft has spent over a decade and an estimated several hundred million dollars pursuing them.

The idea behind topological qubits is to encode quantum information not in the state of a single particle, but in the collective state of a system of particles — specifically, in the braiding of non-abelian anyons. Non-abelian anyons are quasiparticles that exist only in certain two-dimensional materials under extreme conditions (low temperature, high magnetic field). When you exchange (braid) two non-abelian anyons, the quantum state of the system undergoes a unitary transformation that depends only on the topology of the braid — not on the details of the path, not on the speed, not on the timing. This topological protection makes the qubit intrinsically immune to local noise: the environment cannot distinguish the different braid states because they differ only globally, not locally. The error rate, in theory, scales exponentially with the distance between anyons, rather than linearly with time as in conventional qubits.

The specific physical system that Microsoft has been pursuing is based on Majorana zero modes (MZMs) in semiconductor-superconductor nanowires. A Majorana zero mode is a quasiparticle that is its own antiparticle — it is a collective excitation of electrons in a superconducting nanowire that behaves as a non-abelian anyon. Two MZMs form a topological qubit (specifically, a “Majorana qubit” or “topological qubit”).

Here is a simplified device structure:

    +====================================================+
    |         Semiconductor Nanowire (InAs/InSb)          |
    +====================================================+
    |                                                      |
    |   +---------------+         +---------------+        |
    |   | Superconductor |         | Superconductor |        |
    |   | (Al)           |         | (Al)           |        |
    |   +-------+-------+         +-------+-------+        |
    |           |                         |                 |
    |      MZM at end               MZM at end             |
    |           |                         |                 |
    +-----------+-------------------------+-----------------+
                |                         |
          +-----v-----+           +-------v-------+
          |  Gate      |           |  Gate         |
          | (Tunneling)|           | (Tunneling)   |
          +-----------+           +---------------+

The MZMs appear at the ends of the nanowire when it is in the topological phase — which requires a strong spin-orbit coupling (provided by the InAs or InSb semiconductor), proximity-induced superconductivity (from the aluminum layer), and a magnetic field applied parallel to the wire. The presence of an MZM is detected by tunneling spectroscopy: an electron from a normal metal lead tunnels into the nanowire, and the differential conductance shows a zero-bias peak — a signature of the Majorana state.

The challenge — and the reason topological qubits do not yet exist — is that the experimental evidence for MZMs has been contested. In 2018, a team at Delft University of Technology, led by Leo Kouwenhoven (a Microsoft collaborator), published a paper in Nature claiming to have observed quantized zero-bias conductance peaks consistent with MZMs. In 2021, the paper was retracted after other researchers could not reproduce the results and after internal investigations revealed that the data had been “overprocessed” — a diplomatic way of saying that the signal was massaged to look like a Majorana signature. Microsoft has since regrouped, publishing a new paper in 2023 claiming more robust evidence using a different measurement technique (interferometry rather than tunneling spectroscopy), but the broader condensed-matter physics community remains skeptical.

If topological qubits can be realized, the architectural implications are profound. The error rate per gate would be exponentially suppressed, meaning that a topological quantum computer might need only a few hundred physical qubits to achieve fault tolerance, compared to millions for superconducting qubits. The gate times would be slower — braiding operations take microseconds to milliseconds — but the coherence time would be essentially infinite (limited only by quasiparticle poisoning, which is itself exponentially suppressed at low temperature). Microsoft’s bet is that the engineering difficulty of creating topological qubits is worth the payoff of not needing massive error correction. Whether this bet pays off is, as of 2025, still an open question.

5. Other Qubit Technologies: A Brief Survey

A comprehensive architectural survey must mention at least a few other qubit platforms:

Neutral atoms. Like trapped ions, neutral atoms (typically rubidium or cesium) are suspended in a vacuum. But instead of electric fields, they are trapped by optical tweezers — focused laser beams that create a potential well for the atom. Single-qubit gates use microwave or optical pulses. Two-qubit gates use the Rydberg blockade: when one atom is excited to a Rydberg state (a highly excited state with a large orbital radius), it shifts the energy levels of nearby atoms, preventing them from being simultaneously excited. This allows a CNOT-like gate with fidelities comparable to trapped ions. The key architectural advantage of neutral atoms is that optical tweezers can be dynamically reconfigured, allowing arbitrary connectivity — each atom can be moved next to any other atom by steering the tweezers. Companies like QuEra Computing and Pasqal are pursuing this approach.

Silicon spin qubits. A single electron confined in a silicon quantum dot encodes a qubit in its spin state. Silicon spin qubits are attractive because they are fabricated using the same processes as CMOS transistors, potentially allowing integration with classical control electronics. The coherence times are decent (milliseconds for isotopically purified silicon-28), and the gate times are fast (nanoseconds, using electron spin resonance). The challenge is variability: each quantum dot is slightly different, and tuning them to the right operating point requires per-qubit calibration. Intel and the startup Silicon Quantum Computing (in Australia) are pursuing this approach.

Photonic qubits. Photons encode qubits in polarization, time bin, or path. Photonic quantum computing has two major advantages: photons do not decohere (they do not interact with the environment), and they can be transmitted over long distances through optical fibers, making them the natural choice for quantum networking. The challenge is that photons do not interact with each other either, which makes two-qubit gates difficult. Measurement-based (or “fusion-based”) quantum computing, pioneered by the startup PsiQuantum, gets around this by performing entangling measurements on photons using linear optics and photon detectors. The gate is probabilistic — it succeeds with some probability, and if it fails, the qubits are destroyed. PsiQuantum’s approach is to accept this probabilistic nature and use massive multiplexing to achieve determinism at the logical level. This requires millions of physical qubits (photons) and thousands of detectors, but the components are essentially telecom equipment, not exotic cryogenic devices.

6. Quantum Error Correction: The Overhead That Dominates Everything

No physical qubit is perfect. State-of-the-art superconducting qubits have gate error rates of (10^{-3}) to (10^{-4}) per operation. Trapped ions are about 10× better. Topological qubits, if they exist, would be 10,000× better. But even the best physical qubits are not good enough to run Shor’s algorithm on a 2048-bit number — that requires something like (10^{10}) gates with a total error probability below 1%, which implies a per-gate error rate below (10^{-12}).

Quantum error correction (QEC) bridges this gap. The key ideas, developed in the mid-1990s by Shor, Steane, Calderbank, and others, are:

Encode a logical qubit in the entangled state of multiple physical qubits.
Periodically measure stabilizer operators — multi-qubit parity checks that detect errors without collapsing the logical state.
Use the syndrome (the pattern of stabilizer measurement outcomes) to infer which physical qubits have errors.
Apply corrections (or, equivalently, track the errors in software and adjust future measurements).

The surface code is the most practical QEC code for two-dimensional qubit arrays. It encodes one logical qubit in a (d \times d) grid of physical qubits, where (d) is the code distance. The logical error rate scales as (p_{\text{logical}} \propto (p_{\text{physical}} / p_{\text{threshold}})^{d/2}), where (p_{\text{threshold}} \approx 10^{-2}) is the threshold error rate below which increasing (d) improves fidelity. For a physical error rate of (10^{-3}), achieving a logical error rate of (10^{-15}) requires a code distance of about (d = 27), which corresponds to (2 \times 27^2 \approx 1,458) physical qubits per logical qubit (the factor of 2 accounts for data and measurement qubits).

Here is a (d=3) surface code patch:

    D -- X -- D -- X -- D
    |    |    |    |    |
    X -- Z -- X -- Z -- X
    |    |    |    |    |
    D -- X -- D -- X -- D
    |    |    |    |    |
    X -- Z -- X -- Z -- X
    |    |    |    |    |
    D -- X -- D -- X -- D

    D = Data qubit (encodes logical state)
    X = X-type measurement qubit (measures ZZZZ stabilizer)
    Z = Z-type measurement qubit (measures XXXX stabilizer)

Each “X” qubit is an ancilla that measures a 4-body (Z^{\otimes 4}) stabilizer. Each “Z” qubit measures a 4-body (X^{\otimes 4}) stabilizer. The pattern of +1 and -1 measurement outcomes reveals the presence and location of errors.

The overhead of the surface code is staggering. For a useful fault-tolerant quantum computer — say, one that can run Shor’s algorithm to factor a 2048-bit RSA key — the resource estimates from Gidney and Ekerå (2019) suggest that you need roughly 20 million physical qubits, operating for about 8 hours, with a code distance sufficient to suppress logical errors to the (10^{-12}) level. This is a “megaquop” machine, and it is the long-term goal of every quantum computing company.

In the near term, the NISQ era is defined by quantum processors that have enough qubits to do something interesting (50-1,000) but not enough to run full error correction. NISQ algorithms — variational quantum eigensolvers (VQE), quantum approximate optimization (QAOA), and the like — try to extract useful work from imperfect qubits by using shallow circuits and classical optimization. The jury is still out on whether any NISQ algorithm provides a provable speedup over classical methods for real-world problems, and a significant fraction of the quantum computing community believes that the NISQ era is a dead end — that without error correction, quantum computers will never outperform classical ones.

7. The Control Stack: From Pulses to Circuits

The quantum computing stack, from bottom to top, looks like this:

    +----------------------------------------+
    |          Quantum Algorithm             |
    | (Shor, Grover, VQE, QAOA, ...)         |
    +--------------------+-------------------+
                         |
    +--------------------v-------------------+
    |         Quantum Compiler               |
    | (Qiskit, Cirq, tket, ...)              |
    | - Optimization                          |
    | - Transpilation (qubit routing)         |
    | - Gate decomposition                    |
    +--------------------+-------------------+
                         |
    +--------------------v-------------------+
    |         Quantum Control                 |
    | - Pulse generation (arbitrary waveform) |
    | - Calibration (frequency, amplitude)    |
    | - Readout signal processing             |
    +--------------------+-------------------+
                         |
    +--------------------v-------------------+
    |         Physical Qubits                 |
    | (Superconducting / Ions / Atoms / ...)  |
    +----------------------------------------+

The compiler takes a high-level quantum circuit — say, a Qiskit QuantumCircuit object describing gates on logical qubits — and maps it to the physical hardware. This involves several steps:

Gate decomposition: Decompose arbitrary unitary gates into the native gate set of the target architecture. For superconducting qubits, the native gates are typically single-qubit rotations (R_X(\theta), R_Z(\theta)) and two-qubit (CNOT) or (CZ) or (ZX_{\theta}) gates.
Qubit routing: Map logical qubits to physical qubits and insert SWAP gates to satisfy connectivity constraints. This is essentially a graph embedding problem: the circuit’s interaction graph must be embedded in the processor’s coupling graph. Optimal routing is NP-hard, but heuristic algorithms (SABRE, for example) work well in practice.
Optimization: Cancel redundant gates (two adjacent CNOTs cancel), merge adjacent single-qubit rotations, and reschedule gates to maximize parallelism. The optimization pass can reduce circuit depth by 30-50% for typical circuits.
Pulse scheduling: Convert gates to time-ordered sequences of microwave (or laser) pulses, accounting for the finite rise time of the arbitrary waveform generators (AWGs) and the need to avoid crosstalk between adjacent qubits.

The control electronics are themselves a formidable engineering challenge. A 1,000-qubit superconducting processor operating at 4-6 GHz requires thousands of high-bandwidth, low-latency AWG channels, each generating shaped microwave pulses with picosecond timing accuracy. The cables that carry these signals from room temperature to the dilution refrigerator (which cools the qubits to 15 millikelvin) must be chosen carefully: too much thermal conductivity, and the fridge cannot maintain base temperature; too little, and the signals are attenuated to uselessness. This is the “wiring bottleneck,” and it is one of the primary obstacles to scaling superconducting qubits beyond the 1,000-qubit level.

8. The Road to Fault Tolerance

The quantum computing industry is coalescing around a roadmap that looks something like this:

Phase 1 (2020-2025): NISQ processors. 50-1,000 physical qubits, 2-4 nines of gate fidelity, no error correction. Applications: variational algorithms, small-scale simulations of quantum systems, exploratory research.

Phase 2 (2025-2030): Early error correction. 1,000-10,000 physical qubits, logical qubits with modest code distances ((d=3)-(5)), demonstration of “beyond-breakeven” error correction (logical qubit lifetime exceeds physical qubit lifetime). IBM’s Heron (2023) and Flamingo (2024) processors, and Google’s Willow (2024) have demonstrated this milestone.

Phase 3 (2030-2035): Logical quantum processors. 10,000-1,000,000 physical qubits, 10-100 logical qubits with high fidelity, capable of running small instances of quantum algorithms (factoring 256-bit numbers, simulating small molecules).

Phase 4 (2035+): Fault-tolerant quantum computing. Millions of physical qubits, thousands of logical qubits, running Shor’s algorithm at cryptographically relevant scale.

Google’s Willow processor, announced in December 2024, is the most significant advance in Phase 2 to date. Willow has 105 transmon qubits with an average (T_1) of 70 μs and two-qubit gate fidelities of 99.5%. More importantly, the Google team demonstrated exponential suppression of logical errors: as the surface code distance increased from (d=3) to (d=5) to (d=7), the logical error rate decreased by a factor of 2.39 per step — matching the theoretical prediction and providing the first unambiguous demonstration of “quantum error correction below threshold” in a real device. This is a genuine milestone, and it suggests that the surface code approach is viable — if we can figure out how to build processors with thousands of qubits and the control electronics to match.

9. The Quantum-Classical Interface

A practical quantum computer will not operate in isolation. It will be an accelerator — like a GPU or an FPGA — attached to a classical host system. The host dispatches quantum circuits, waits for results (or polls for completion), and integrates the quantum outputs into a larger classical computation. This accelerator model, sometimes called the “quantum processing unit” (QPU) model, raises architectural questions that are just beginning to be explored.

The latency of dispatching a quantum circuit is currently dominated by the compilation and pulse-scheduling steps, which can take seconds for a circuit with hundreds of qubits. For variational algorithms, where the classical optimizer iteratively adjusts circuit parameters based on measurement results, this compilation latency is incurred on every iteration, and a single VQE run can require thousands of iterations. Optimizing the compilation pipeline — caching compiled circuits, pre-scheduling pulses for known patterns, performing some compilation steps online in hardware — is an active area of research.

The bandwidth of reading out qubits is another bottleneck. A single qubit measurement produces one bit (or, in the case of mid-circuit measurement with feedforward, one bit that must be processed immediately to determine subsequent gates). A 1,000-qubit processor running a circuit with 10,000 measurements per second produces 10 Mbps of measurement data, which is trivial for classical systems. But the latency of processing that data — decoding the error syndrome and determining corrections — is subject to a strict real-time constraint: the syndrome must be decoded before the next round of stabilizer measurements, which is typically 1-10 μs. This drives the need for low-latency, hardware-accelerated syndrome decoders — an FPGA or ASIC sitting next to the quantum processor in the dilution refrigerator.

10. Summary

Quantum computing is at a fascinating inflection point. After three decades of theoretical development and two decades of experimental progress, we have working quantum processors with hundreds of qubits, gate fidelities approaching the error correction threshold, and the first experimental demonstrations of logical error suppression. We also have a clear roadmap to fault tolerance — a roadmap that requires scaling physical qubit counts by three to six orders of magnitude, which is daunting but not unprecedented in the history of computing (DRAM capacity has scaled by nine orders of magnitude since the 1970s).

The architectural questions are no longer “can we build a qubit?” but “how do we scale a quantum computer?” — the connectivity topology, the control stack, the error correction code, the quantum-classical interface. These are systems problems, and they will be solved by systems thinking.

Whether the NISQ era produces commercially valuable results before fault tolerance arrives is an open question — and, honestly, a bit of a bet. My own view is that NISQ algorithms are intellectually valuable but commercially overhyped, and that the real revolution will come when we have fault-tolerant logical qubits. The good news is that, based on the trajectory of the last five years, that revolution may be closer than skeptics think. The bad news is that “closer” still means “a decade or more.” Quantum computing is a marathon, not a sprint, and we are somewhere around mile 10 of 26.

For the systems researcher looking to engage with quantum computing, my advice is this: do not try to become a quantum physicist. The field needs people who understand the classical side of the interface — compilers, control systems, error decoders, benchmarking methodologies. The quantum stack is full of classical problems that are intellectually deep and practically urgent. How do you schedule gates on a surface code lattice? How do you compile a quantum circuit to minimize depth given connectivity constraints? How do you design a real-time syndrome decoder that runs in 1 μs? These are systems problems, not physics problems, and they are wide open for research. The quantum future will be built as much by computer architects and systems engineers as by physicists. The invitation is open.

11. Quantum Benchmarking and the Supremacy Debate

Measuring quantum computer performance is surprisingly subtle. Classical computers have well-established benchmarks (SPEC, LINPACK, STREAM) that measure throughput on standardized workloads. Quantum computers have no such consensus. The debate around “quantum supremacy” — the claim that a quantum computer has solved a problem that no classical computer can solve in a feasible amount of time — illustrates the difficulty.

Google’s 2019 Sycamore experiment was the most prominent supremacy claim: a 53-qubit processor performed a random circuit sampling task in 200 seconds that Google estimated would take 10,000 years on the world’s largest classical supercomputer. IBM immediately disputed the claim, arguing that with optimized tensor network contraction algorithms and sufficient disk storage, the same computation could be performed in 2.5 days on a classical supercomputer — not 10,000 years. The dispute hinged on the definition of “feasible”: does 2.5 days count as infeasible? If so, quantum supremacy was not achieved.

The deeper problem is that random circuit sampling is a contrived task with no known practical application. It was chosen specifically because it is hard for classical computers and (relatively) easy for near-term quantum processors. A true demonstration of quantum advantage — a quantum computer solving a commercially valuable problem faster, cheaper, or more accurately than a classical computer — remains elusive. The most promising near-term candidates are quantum simulation (modeling molecules for drug discovery or materials science) and quantum machine learning, but both require fault-tolerant logical qubits that do not yet exist.

The benchmarking community is developing standardized metrics: quantum volume (IBM’s proposal, measuring the largest random circuit of equal width and depth that a processor can run successfully), CLOPS (circuit layer operations per second, measuring throughput), and algorithmic qubits (the number of useful qubits after accounting for error rates). These metrics provide a more nuanced picture than raw qubit count, but they are not yet standardized across vendors, making cross-platform comparisons difficult. This is a systems measurement problem that will become increasingly important as quantum processors move from research labs to production data centers.