Calendar
Posts organized
by date.00:00
Building A Custom Risc V Processor In Verilog: Pipelining, Hazard Detection, And Branch Prediction
00:00A comprehensive technical exploration of building a custom risc v processor in verilog: pipelining, hazard detection, and branch prediction, covering key concepts, practical implementations, and real-world applications.
JIT Compilation: Tracing vs Method JITs, V8's Ignition+TurboFan Pipeline, HotSpot's C1/C2 Tiered Compilation, and Deoptimization
A deep exploration of just-in-time compilation — how V8 and HotSpot turn JavaScript and Java bytecode into native code through multi-tier compilation pipelines, and the art of deoptimization that makes speculative optimization safe.