Hardware-Architecture
8 posts in category “Hardware-Architecture”.
Storage-Class Memory: Intel Optane, 3D XPoint, and the Lessons of a Bold Failure
2025-08-15The technology, the programming model, and the performance characteristics of Intel Optane — and why the most promising memory technology in a generation failed commercially despite delivering exactly what it promised.
Memory Technologies: DRAM, HBM, GDDR, and the Scaling Wall
2025-08-10Inside the memory hierarchy that feeds the compute engines — DRAM cell physics, HBM stack architecture, GDDR for graphics, the row hammer crisis, and emerging alternatives like FeRAM and MRAM.
ASIC Design Flow: From RTL to GDSII — Synthesis, STA, and the Tapeout Checklist
2025-06-22A walk through the entire ASIC design flow — logic synthesis with Design Compiler, static timing analysis with PrimeTime, place-and-route with Innovus/ICC2, clock tree synthesis, and the signoff checklist that separates working silicon from a very expensive coaster.
FPGA Programming: HLS, Verilog, and the Spatial Computing Paradigm
2025-05-12How reconfigurable hardware rewires the boundary between software and silicon — from Verilog's explicit dataflow to high-level synthesis with C++, and why FPGAs are eating the inference and networking world.
Quantum Computing Architectures: Superconducting Qubits, Trapped Ions, and the NISQ Era
2025-04-17From transmon Hamiltonians to Majorana zero modes — a deep architectural dive into the physical platforms competing to build the first fault-tolerant quantum computer, and why the error correction overhead dominates everything.
CHERI and Capability Hardware: Memory Safety at the Gate Level
2025-03-11How CHERI Concentrate compression, the load barrier for temporal safety, and the Arm Morello prototype are reshaping what it means to build a secure processor — and why formal verification of capability integrity is the hard part.
RISC-V: The Open ISA Revolution and the Cambrian Explosion of Processor Design
2025-02-11How a Berkeley research project became the Linux of instruction sets, rewiring the economics of custom silicon from embedded MCUs to vector supercomputers with the RVV extension and the CHERI security story.
Processing-in-Memory: UPMEM, Samsung HBM-PIM, and the Near-Data Computing Paradigm
2025-02-10How moving compute to where the bits live rewrites the rules of memory-bound computation, from UPMEM's DRAM-scale PIM to Samsung's HBM-PIM and the programming model that still keeps us up at night.