#Cheri
3 posts in tag “Cheri”.
CHERI and Capability Hardware: Memory Safety at the Gate Level
2025-03-11How CHERI Concentrate compression, the load barrier for temporal safety, and the Arm Morello prototype are reshaping what it means to build a secure processor — and why formal verification of capability integrity is the hard part.
RISC-V: The Open ISA Revolution and the Cambrian Explosion of Processor Design
2025-02-11How a Berkeley research project became the Linux of instruction sets, rewiring the economics of custom silicon from embedded MCUs to vector supercomputers with the RVV extension and the CHERI security story.
Capability-Based Security: CHERI Architecture, Hardware Capabilities, Spatial and Referential Safety, and Compartmentalization
2021-02-26A deep exploration of the CHERI capability architecture — how hardware-enforced capabilities provide spatial memory safety, referential integrity, and fine-grained compartmentalization at the instruction level.