Computer-Architecture

• CHERI and Capability Hardware: Memory Safety at the Gate Level · 2025-03-11

  How CHERI Concentrate compression, the load barrier for temporal safety, and the Arm Morello prototype are reshaping what it means to build a secure processor — and why formal verification of capability integrity is the hard part.

• RISC-V: The Open ISA Revolution and the Cambrian Explosion of Processor Design · 2025-02-11

  How a Berkeley research project became the Linux of instruction sets, rewiring the economics of custom silicon from embedded MCUs to vector supercomputers with the RVV extension and the CHERI security story.

• Processing-in-Memory: UPMEM, Samsung HBM-PIM, and the Near-Data Computing Paradigm · 2025-02-10

  How moving compute to where the bits live rewrites the rules of memory-bound computation, from UPMEM's DRAM-scale PIM to Samsung's HBM-PIM and the programming model that still keeps us up at night.

• VLIW and EPIC: The Multiflow Trace, Itanium, and Why Static Scheduling Lost to Out-of-Order · 2024-01-14

  A historical and technical analysis of VLIW and EPIC architectures—the Multiflow Trace, Intel Itanium—examining static scheduling, predication, rotating registers, and why out-of-order superscalar won the commercial battle.