#Microarchitecture
6 posts in tag “Microarchitecture”.
CPU Microarchitecture: Pipelines, Out-of-Order Execution, and Modern Performance
2025-12-04An in-depth exploration of CPU microarchitecture: instruction pipelines, hazards, branch prediction, out-of-order execution, register renaming, superscalar and SIMD units, and how software maps to hardware for performance.
Simultaneous Multithreading: Resource Sharing, Security Implications, and the SMT Performance-Security Tradeoff
2024-02-01A deep dive into SMT/Hyper-Threading: how frontend and backend resources are shared between threads, the security vulnerabilities like PortSmash and TLBleed, and the evolving performance-security tradeoff.
Superscalar Processors: Register Renaming, Reorder Buffers, and How Modern Cores Extract ILP
2023-09-28A microarchitectural deep dive into superscalar execution: register renaming, the reorder buffer, reservation stations, and the issue queue, examining how Haswell, M1, and Zen4 extract instruction-level parallelism from sequential code.
Microarchitectural Attacks: Spectre, Meltdown, and the Transient Execution Apocalypse
2023-04-06A deep analysis of Spectre v1-v4, Meltdown, and the root cause in speculative execution, covering the endless cycle of mitigations and new attack variants that exploit the microarchitectural state.
Branch Prediction and Speculative Execution: How Modern CPUs Gamble on the Future
2021-08-15Explore how modern processors predict branch outcomes and execute instructions speculatively, the algorithms behind branch predictors, the performance implications for your code, and the security vulnerabilities like Spectre that emerged from these optimizations.
Speculative Prefetchers: Designing Memory Systems That Read the Future
2019-02-14A field guide to building and validating speculative memory prefetchers that anticipate demand in modern CPUs and data platforms.